1. Field of the Invention
The present invention relates generally to jitter compensation circuits, and more particularly, a jitter compensation circuit for processing jitter components included in a video signal, for example, a high definition television (HDTV) signal reproduced by a video signal reproducing apparatus such as a video tape recorder (refered to as VTR hereinafter) and a video disc player.
2. Description of the Background Art
In general, a reproduced video signal outputted from a video signal reproducing apparatus such as a VTR and a video disc player is subjected to fluctuation in time due to various causes. Such fluctuation in time is generally referred to as "jitter". Taking a VTR as an example, jitter components are included in a reproduced video signal due to various causes such as the fluctuation of a tape travelling speed, irregular rotation of a cylinder and the vibration of a tape in traveling at the time of recording and/or reproducing of the video signal to and from the tape. Allowing such jitter components causes flickering of picture and unevenness of color, which deteriorate the picture quality. Therefore, a conventional video signal reproducing apparatus is usually provided with a correction circuit for jitter components. As an example of such a jitter compensation circuit, the circuit adapted for a VTR is disclosed in Japanese Patent Laying-Open No. 58-124385.
FIG 1 is a schematic block diagram showing such a conventional jitter compensation circuit for VTR. In FIG. 1, a jitter compensation circuit 100 built in the VTR itself receives a reproduced video signal from a video signal reproducing circuit 200 of the VTR to subject the same to the jitter compensation which will be described later, then externally outputs the jitter corrected video signal as a reproduced video signal output of the VTR through an external output terminal 300 of the VTR to supply the same to a display device (not shown) such as a monitor TV.
Briefly state, the jitter compensation circuit 100 shown in FIG. 1 corrects jitter components in a reproduced video signal roughly by controlling the timing for starting to write an A/D converted reproduced video information to a memory every horizontal line, and furthermore corrects jitter components finely by controlling the timing for A/D convertng the reproduced video signal. In order to perform such a jitter compensation, first the amount of jitter in the reproduced video signal should be detected. Such detection of the jitter amount is carried out by detecting a phase shift of a burst signal considering that a level of the burst signal in the A/D converted reproduced video signal corresponds to the phase shift of the video signal itself.
FIG. 2 is a timing chart for explaining an operation of the jitter compensation circuit 100 shown in FIG. 1. With reference to FIGS. 1 and 2, a structure and an operation of the conventional jitter compensation circuit will be described in the following.
First, a reproduced video signal applied from the video signal reproducing circuit 200 of FIG. 1 to the jitter compensation circuit 100 is comprised of a negative horizontal synchronizing signal H.sub.SYNC, a burst signal and a video signal (including time base compressed color signal C and luminance signal Y) in one horizontal (H) period as shown in FIG. 2 (a), wherein the horizontal synchronizing signal and the burst singla are included in a horizontal blanking period.
The reproduced video signal is first applied to an A/D converter 7 wherein the signal is A/D converted in synchronization with a reference clock supplied from a reference clock generating circuit 17. Then, an output of the A/D converter 7 is applied to a synchronization separating circuit 8 and a jitter detection circuit 9. The synchronization separating circuit 8 detects a timing for the horizontal synchronizing signal from the applied video signal, and at which timing generates a negative synchronization separating pulse (FIG. 2 (b)). Usually a fixed delay is attendant from the time of timing detection to pulse generation. The pulse is applied to a burst flag generating circuit 10 and a fixed delay circuit 11.
The burst flag generating circuit 10 starts counting of reference clock pulses applied from the reference clock generating circuit 17 in response to the applied pulse (FIG. 2 (b)). Then, when the counted value reaches a predetermined value, the burst flag generating circuit 10 generates a burst flag pulse as shown in FIG. 2 (c) and applies the same to the jitter detection circuit 9. A rise timing and a duration of the burst flag pulse is predetermined so as to correspond to a generation period of, for example, burst waves of four periods in the middle which are obtained by eliminating the waves on both sides of, for example, burst waves of six periods constituting the burst signal.
The fixed delay circuit 11 also starts counting of the reference clock pulses applied from the reference clock generating circuit 17 in response to the applied pulse (FIG. 2 (b)). Then, when the counted value reaches a predetermined value, that is, at a timing which is after the end of the burst period and immediately before the start of a video signal period, the fixed delay circuit 11 generates the pulse as shown in FIG. 2 (d) and applies the same to a writing start control circuit 13 which will be described later.
The jitter detection circuit 9 detects sampling phases of the burst signal from levels of the output of the A/D converter 7 (i.e. burst wave) during the burst flag pulse generation period. If the fluctuation in time, that is, a phase shift occurs in the reproduced video signal, sampling point of the burst wave fluctuates at the time of A/D conversion, so that a level at each sampling point is fluctuated. Accordingly, the jitter detection circuit 9 calculates the sampling phase based on such a sampling level and outputs a mean value of sampling phases corresponding to four waves as a signal corresponding to the amount of the phase shift, that is, the jitter amount of the video signal.
Jitter occurs within the range of .+-. n clock when a frequency of the reference clock is 2n (n is a positive integer) times as large as a burst frequency. Therefore, the jitter amount detected by the jitter detection circuit 9 is within this range.
The detection data outputted from the jitter detection circuit 9 is, for example, 8 bit data, most significant three bits of which being applied to the writing start control circuit 13 for use in the correction of large jitter components (corresponding to integer number of reference clock periods), as will be described later, and leas significant 5 bits of which being applied to a clock phase modulating circuit 12 and a timing circuit 2 for use in the correction of small jitter components (corresponding to a period smaller than one period of the reference clock) as will be described later.
The clock phase modulating cirucit 12 is a circuit for modulating a phase of the reference clock supplied from the reference clock generating circuit 17. Then, the reproduced video signal supplied from the video signal reproducing circuit 200 is also applied to the A/D converter 1 wherein the signal is A/D converted in synchronization with the phase modulated clock outputted from the clock phase modulating circuit 12. On this occasion, the phase modulating circuit 12 immediately controls a phase shift amount of the reference clock so as to correct a phase shift smaller than one clock period, based on the low-order data of the detection data from the above described jitter detection circuit 9.
Then, the output of the A/D converter 1 is applied to the timing circuit 2. Briefly stated, the timing circuit detects a specific phase relation based on the detection data from the jitter detection circuit 9, thereby controlling the timing for transferring the A/D converted data, considering the fact that reliable transfer of the A/D conversion data becomes difficult when a phase relation between the above described reference clock and the phase modulated clock becomes a specific one. FIG. 3 is a block diagram showing a structure of the timing circuit 2 and FIGS. 4A and 4B are timing charts for explaining an operational principle thereof.
More specifically, the timing circuit 2 is comprised of a latch circuit 2a for latching the output (FIG. 4 (c)) of the A/D converter 1, a timing switching circuit 2b responsive to a phase modulated clock (FIG. 4(a)) from the clock phase modulating circuit 12 of FIG. 1 for subjecting the phase modulated clock to a code inversion processing and the like, based on jitter detection data from the jitter detection circuit 9, to supply a timing clock (FIG. 4(b)) to the latch circuit 2a, and a D-flip-flop 2c operating in response to a reference clock (FIG. 4(d)). In the circuit of FIG. 3, the timing switching circuit 2b usually applies the phase modulated clock directly to the latch circuit 2a as shown in FIG. 4A(a) and (b), which circuit latches the A/D converted data (FIG. 4A(c)) at the timing. For example, as shown in FIG. 4A (a), assuming that the A/D converted data (FIG. 4A (c)) is latched in the latch circuit 2a at a rise timing of the phase modulated clock and the data thereof is written in the D-Flip-flop 2c at the rise timing of the reference clock as shown in FIG. 4 (d). However, in case of the phase relation as shown in FIG. 4A, transferring to the D-flip-flop 2c is performed during the writing of the video data, so that precise data transferring can not be implemented. Therefore, in case the phase relation as shown in FIG. 4A occurs, by shifting the timing clock for writing to the latch circuit 2a by 1/2 period without changing the timing for A/D conversion, as shown in FIG. 4B, data transfering to the D-flip-flop 2c can be reliably performed.
Accordingly, the timing circuit 2 of FIG. 3 is structured such that the phase modulated clock is shifted by 1/2 period through code inversion to be applied to the latch circuit 2a in case the jitter detection data shows the specific phase relation as shown in FIG. 4A.
The output of the timing circuit 2 is delayed through a video delay circuit 3 so as to compensate the time delay attendant with the above described horizontal synchronization detection, and thereafter written into a memory 4. Writing and reading operations of the memory 4 are controlled by a writing control circuit 14 and a reading control circuit 16 respectively. Then, the timing for starting to write data in the memory 4 is defined by a write starting pulse applied from the writing start control circuit 13 to the writing control circuit 14.
Described in more detail, the writing start control circuit 13 starts counting of the reference clock pulses in response to a pulse from the fixed delay circuit 11 (FIG. 2(d)), then, when the counted value reaches the value determined by the contents of the high-order data among the detection data from the jitter detection circuit 9, generates a write starting pulse (variable delay pulse) as shown in FIG. 2 (e) and applies the same to the writing control circuit 14. Namely, the writing start control circuit 13 appropriately and variably delays a fixed delay output (FIG. 2 (d)) by the amount of time corresponding to the magnitude of the jitter at that time. As a result, the write starting pulse (FIG. 2 (e)) synchronizes with a starting point of a video signal period in every 1H period irrespective of the degree of jitter, so that only the video information in each horizontal line is written into the memory 4 under the control of the writing control circuit 14.
Subsequently, the timing for starting to read the video information for every horizontal line written in the memory 4 is defined by a read starting pulse applied from a read H generating circuit 15 to a reading start control circuit 16, so that the contents of the memory 4 is read out in synchronization with the reference clock under the control of the reading control circuit 16.
The video information read out from the memory 4 is D/A converted by a D/A converter 5 in synchronization with the reference clock and then externally outputted as a reproduced video signal through the terminal 300.
Although the prior art shown in FIG. 1 comprises two A/D converters 1 and 7, these A/D converters need not be operated simultaneously. Accordingly, one A/D converter may be provided such that a clock to be inputted is switched between the horizontal blanking period and the video signal period in order to implement the same operation as that of the prior art of FIG. 1.
FIG. 5 is a schematic block diagram showing one example of a conventional jitter compensation circuit including only one A/D converter as described above.
The prior art shown in FIG. 5 is the same as the prior art shown in FIG. 1 except for the following points. Namely, in FIG. 5, the A/D converter 7 of FIG. 1 is not provided and the reproduced video signal which is A/D converted in the A/D converter 1 and further passed through the timing circuit 2 is applied to the synchronization separating circuit 8 and the jitter detection circuit 9. The synchronization separating circuit 8, as the prior art of FIG. 1, detects a horizontal synchronization timing in the reproduced video signal and applies a pulse synchronized therewith to a clock switching circuit 18 as well as to the burst flag generating circuit 10 and the fixed delay circuit 11. Operations of the burst flag generating circuit 10 and the fixed delay circuit 11 are the same as those of FIG. 1 described above.
Furthermore, the clock commonly supplied to the A/D converter 1 and the timing circuit 2 is selected by a first switch S.sub.1. Switching of the switch S.sub.1 is controlled by the foregoing clock switching circuit 18. More specifically, the clock switching circuit 18 switches the switch S.sub.1 to the side of a terminal b during the horizontal blanking period in response to the output of the synchronization separating circuit 8, whereby a reference clock from the reference clock generating circuit 17 is supplied to the A/D converting circuit 1 and the timing circuit 2. In addition, a switch S.sub.2 which is switched linking with the switch S.sub.1 is further provided, and whcih switch S.sub.2 is also switched to the side of the termianl b during the horizontal blanking period, thereby interrupting the supply of the jitter compensation data to the timing circuit 2.
In this way, during the horizontal blanking period, the reproduced video signal which is A/D converted by the reference clock is applied to the jitter detection circuit 9 through the timing circuit 2, then the jitter detection circuit 9 generates jitter detection data based on a mean value of the sampling phase of the burst in the burst flag pulse generation period, as the embodiment of FIG. 1. Then, the writing start control circuit 13 defines a timing for starting to write of he video information to the memory 4, based on the high-order data of the jitter detection data, and the phase clock modulating circuit 12 determines a shift amount of the phase modulated clock, based on the low-order data thereof.
When the horizontal blanking period ends and the video signal (C and Y) period starts, both of the switches S.sub.1 and S.sub.2 are switched to the terminal a side by a signal from the clock switching circuit 18. As a result, a phase modulated clock is supplied from the clock phase modulating circuit 12 through the switch S.sub.1 to both of the A/D converter 1 and the timing circuit 2, and furthermore the low-order data of the jitter detection data is supplied from the jitter detection circuit 9 through the switch S.sub.2 to the timing circuit 2.
More specifically, in the prior art of FIG. 5, during the horizontal blanking period, a jitter amount is detected based on the reference clock, and during the video signal period, the reproduced video signal is A/D converted in synchronization with the clock corrected based on the amount of jitter and the A/D converted data is written into the memory 4 at a timing defined based on the amount of jitter.
However, the prior art shown in FIG. 5 requires the switches S.sub.1 and S.sub.2 to be switched without fail before and after the horizontal blanking period, which might prevent a precise jitter compensation. For example, due to a switching from the phase modulated clock to the reference clock by the switch S.sub.1 immediately before the horizontal blanking period, a timing for sampling by the A/D converter 1 is changed, which might prevent a precise detection of a horizontal synchronization timing in the synchronization separating circuit 8. Such a failure of the detection of the horizontal synchronization timing might prevents a burst period from being determined and the jitter amount from being detected, which makes a precise jitter compensation impossible. In addition, there exist possibility that the video information to be written into memory 4 might be affected due to switching from the referene clock to the phase modulated clock by the switch S.sub.1 at the timing of switching from the horizontal blanking period to the video signal period.